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Image of - Pipelined Multiprocessor System-on-Chip for Multimedia | Hardcover
Pipelined Multiprocessor System-on-Chip for Multimedia | Hardcover

Pipelined Multiprocessor System-on-Chip for Multimedia | Hardcover

by Javaid

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

Highlights

  • binding-icon

    9783319011127

    ISBN:

  • binding-icon

    Javaid

    Author:

  • binding-icon

    169

    Pages:

  • binding-icon

    215 gm

    Weight:

  • langauage-icon

    English

    Language:

  • date-icon

    2014

    Year:

  • edition-icon

    N/A

    Edition:

  • binding-icon

    Hardcover

    Binding:

₹10508

₹13135

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

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